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Critical Net Design & Analysis
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A three-dimensional IC critical net field simulator for creat- ing very accurate RCLK SPICE decks of selected nets on IC. NET-AN graphically extracts, builds a 3D model, and simulates a net, tree, or critical path allowing the user or the system to automatically assign nodes. |
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A tool for exploring the design space of a process technology as it relates to interconnect design limits and interconnect behavior. BUS-AN performs a variety of pre-design explorations such as inductive shielding effects, buffering strategies, clock-tree prototyping, and process corner simulations. |
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A VLSI floorplanning tool for the fast design and optimiza-tion of clock networks at the block or full chip level. |
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RF Component Design & Analysis
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A design tool set for creating optimal embedded spiral inductor designs in ICs, Hybrids, and PCBs. It integrates together geometry building engine, a 2-D and 3-D field solver for extraction of RCL, and a frequency dependent circuit simulator. Outputs include GDSII, graphical plot file, SPICE models, and S- and Z- parameter files. |
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RF-PASS is designed to assist RF engineers in accurately synthesizing, optimizing and modeling inductors, transformers, capacitors and resistors for RFIC applications. RF-PASS can also be used in modeling large distributed structures such as bond pads and ESD devices. |
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Power System Design & Analysis |
A VLSI power distribution network floor- planning tool used with P-GRID for optimizing the geometric configuration of VDD and VSS rings, internal power rails, and ring voltage source pad locations using estimated block current sources. |
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A three-dimensional power network simulator for analyzing the power or ground networks on an IC. P-GRID extracts, builds a 3-D model, and simulates a power network reporting errors in voltage or current density levels. |
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A program for optimizing the design of VLSI power distribution I/O rings. Common problems of ground bounce and simultaneous switching noise are easily debugged and solutions found by fast turn around what-if analysis. |
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Cell Library Parasitic Extraction
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A three-dimensional level SPICE extraction that generates a cell or macro sub-circuit with significant RC, S/D resistances and geometry dependent transistor SPICE models. |
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Packaging Analysis |
A three-dimensional inductance simulator that calculates inductance and mutual inductance of any interconnect structure in electronic media. |
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A field simulator for extracting metal parasitics from interconnect and IC structures. It features automatic mesh generation and refinement, and automatic SPICE sub-circuit generation. |
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Consultancy |
We work closely with companies as consultants to help solve specific design problems, so we work on their most advanced designs while they are being created. This keeps us on the leading edge of technology, and helps us anticipate industry needs. Please email: info@oea.com or call (408) 778-6747 |
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