60nm and 90nm Interconnect Modeling Challenges. FSA 2004, Design Modeling Workshop. By Ersed Akcasu.
Click here to download pdf file
Practical Multi-Gigahertz Clocks for ASIC and COT Designs. By Haris Basit, John Wood, and Kenneth Pedrotti.
Click here to download pdf file
A Practical Approach to Preventing Simultaneous Switching Noise and Ground Bounce Problems in IO Rings. By Ersed Akcasu, Jerry Tallinger, and Kerem Akcasu.
Click here to download pdf file
Tools for On-Chip Interconnect Inductance Extraction. By Jerry Tallinger and Haris Basit.
Click here to download pdf file
Spiral and RF-PASS Three Dimensional Design and Analysis Tools for RF Integrated Circuits. By Ersed Akcasu, Haris Basit, Kerem Akcasu, Tufan Colak and Ibrahim Akcay.
Click here to download pdf file
A General and Comparative Study of RC(0), RC, RCL and RCLK Modeling of Interconnects and their Impact on the Design of Multi-Giga Hertz Processors.By Ersed Akcasu, Onur Uslu, Nagaraj Ns, Tufan Colak, Stephen Hale, and Edmund Soo.
Click here to download pdf file
Optimization of Metal-Metal Comb-Capacitors for RF Applications.By Jay Pajagopalan and Haris Basit.
Click here to download pdf file
NET-AN a Full Three Dimensional Parasitic Interconnect Distributed RCL Extractor for Large Full Chip Applications. By Ersed Akcasu, Jesse Lu, Alexander Dalal, Sundari Mitra, Hem Hingarh, and Haris Basit.
Click here to download pdf file
Case Study of On-Chip Inductance Effects (Extraction and Analysis). By Ersed Akcasu